Large-scale (multi-million gate) application specific integrated circuit (“ASIC”) designs are hampered by many logistical problems. Many of these problems are related to the functional integration, timing, and testing of various sub-modules at the top level of the ASIC design. If sub-module design changes are required to remedy top-level timing issues, for example, costly delays and recursive design changes can result. Design changes of this nature drive up engineering, manufacturing and test costs for ASIC manufacturers.
Further, ASIC designs typically have limited reconfigurability, which is to say they may be programmable via control registers, but they use fixed architectures. These fixed architectures do not allow for functional modules to be re-arranged or reconfigured by a user. ASICs such as field programmable gate arrays (“FPGAs”) permit the user to reconfigure or reprogram functional modules, however, they are an extreme example which require a great deal of specialized programming and a special, fine-grained ASIC architecture to implement.
Within the current state of the art for ASIC design, manufacture, and test, there does not exist an architecture that may provide easy top-level integration of modules, routing, and timing, all within a standardized I/O scheme. Hence there is a need for an advanced ASIC architecture to address one or more of the drawbacks identified above.